1. Technical Field
The present invention relates to semiconductor memory apparatus, and more particularly, to an apparatus and method for controlling an active period of semiconductor memory apparatus.
2. Related Art
In general, in a semiconductor memory apparatus, the entire memory cell is divided by banks in order to easily perform data read and write operations and other operations related to the data read and write operations. With the development of technology, the capacity of memory is increasing, which causes the number of banks to increase.
A large number of banks causes an increase in current consumption. Therefore, a method of reducing current consumption is needed.
Hereinafter, an apparatus for controlling an active period of semiconductor memory apparatus according to the related art will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram illustrating the configuration of the apparatus for controlling an active period of a semiconductor memory apparatus according to the related art. FIG. 2 is a circuit diagram illustrating the internal structure of an active control unit shown in FIG. 1. FIG. 3 is a circuit diagram illustrating the internal structure of an active signal generating unit shown in FIG. 1.
As shown in FIG. 1, the apparatus for controlling an active period of a semiconductor memory apparatus according to the related art includes an active controller 10 that generates an active control signal for determining the active period of each bank, a precharge signal generator 20 that generates a precharge signal for each bank by using the active control signal, and an active signal generator 30 that generates an active signal for each bank by using the active control signal.
FIG. 1 shows a structure having four banks B0 to B3.
The active controller 10 includes first to fourth active control units 11 to 14 for generating active control signals TRASMIN0 to TRASMIN3, respectively. The first to fourth active control units 11 to 14 have the same structure, and the internal structure of the first active control unit 11 is described below as a representative example. As shown in FIG. 2, the first active control unit 11 includes an inverter 15 that inverts an active signal BA0_DLY delayed by a predetermined amount of time, a NAND gate 16 that receives the output of the inverter 15 and a high-level power supply signal VDD, an inverter 17 that inverts the output of the NAND gate 16, and a delay element 18.
The precharge signal generator 20 includes first to fourth precharge signal generating units 21 to 24 for generating precharge signals APCG0 to APCG3 on the basis of the active control signals TRASMIN0 to TRASMIN3, respectively.
The active signal generator 30 includes first to fourth active signal generating units 31 to 34 for generating active signals BA0 to BA3 for the active control signals TRASMIN0 to TRASMIN3, respectively. The first to fourth active signal generating units 31 to 34 have the same structure, and the internal structure of the first active signal generating unit 31 is described below as a representative example. As shown in FIG. 3, the first active signal generating unit 31 includes: a first NOR gate 31-1 that receives a pulse FACT0 generated according to an external active instruction and a pulse ACT0 generated according to an internal active instruction and determines whether to output the active signal; a second NOR gate 31-2 that receives a reset signal RST and a precharge signal PRE0 and determines whether to output the active signal; a third NOR gate 31-3 that receives an auto-precharge signal APCG0 and the active control signal TRASMIN0 and determines whether to output the active signal; a latch 31-4 that holds the output of the first NOR gate 31-1 on the basis of the output of the second NOR gate 31-2 or the third NOR gate 31-3; and a driver 31-5 that drives the output of the latch 31-4.
Each of the precharge signals APCG0 to APCG3 are input to the first to fourth active signal generating units 31 to 34, respectively. In addition, each of the active signals BA0 to BA3 are input to the first to fourth active control units 11 to 14, respectively.
The operation of the apparatus having the above-mentioned structure according to the related art will be described below.
The first to fourth active control units 11 to 14 of the active controller 10 output the active control signals TRASMIN0 to TRASMIN3, respectively.
Then, the first to fourth precharge signal generating units 21 to 24 of the precharge signal generator 20 generate the precharge signals APCG0 to APCG3 on the basis of the active control signals TRASMIN0 to TRASMIN3, respectively.
The first to fourth active signal generating units 31 to 34 of the active signal generator 30 generate the active signals BA0 TO BA3 so as to be suitable for the active control signals TRASMIN0 to TRASMIN3, respectively, and supply the generated active signals BA0 TO BA3 to a circuit for driving word lines corresponding to the banks B0 to B3.
The active control signals TRASMIN0 to TRASMIN3 are signals for determining the active periods of the active signals BA0 to BA3, for example the end times of high level periods, respectively. After the active control signals TRASMIN0 to TRASMIN3 turn to a high level and then a predetermined time delay occurs, the active signals BA0 to BA3 are disabled.
Meanwhile, in a semiconductor memory apparatus, particularly a DRAM, cell data is damaged with time due to structural characteristics. Therefore, a refresh operation is required to prevent damage.
The refresh operations are divided into an auto-refresh operation that is performed according to instructions from an external system of the semiconductor memory apparatus and a self-refresh operation that is performed in the semiconductor memory apparatus. The auto-refresh operation and the self-refresh operation are performed on the banks at the same time. That is, the auto-refresh operation and the self-refresh operation are performed on all the banks, not a specific bank.
However, the semiconductor memory apparatus according to the related art has the following problems.
First, each active control unit generates a separate active control signal for each active signal generating unit during the refresh operation. Therefore, current consumption increases during the refresh operation. In addition, the larger the number of banks becomes, the higher current consumption becomes.
Second, additional signal lines for supplying the active control signals to the active signal generating units are needed. Therefore, the arrangement of the signal lines is complicated. In addition, the larger the number of banks becomes, the more complicated the arrangement of signal lines becomes.